System Addressing

• Address Space Overview
• CPU Address Map
• CPU to PCI Map
• CPU to PCI I/O Space
• PCI Space 0 Mapping
• PCI Space 1 Mapping
• TIG Address Space Translation
• PCI DMA Address Translation
• Monster Window

Address Configuration

From the CPU’s perspective the PCI I/O and memory space are linear and byte accessible. Since the Alpha 21264 processor supports byte mode accesses, we can default to a single linear I/O space.

The PCI host controller in the P-Chip does not recognize I/O space accesses directed at it from other PCI or ISA devices.

The TIG Address is sparse in that each aligned 64 byte region has only 1 byte of information.

CPU Address Map

SPACE	SIZE	CPUAddr[43:0]	Notes
System Memory	2 GB	000 0000 0000 000 FFFF FFFF	Cacheable, Pre-fetchable.
Reserved	8188 GB	001 0000 0000 7FF FFFF FFFF
P-Chip0 PCI Memory	4 GB	800 0000 0000 800 FFFF FFFF	Linear Addressing, Non-Cacheable.
TIG BUS	1 GB	801 0000 0000 801 3FFF FFFF	addr[5:0]=0. 1 byte/64bytes. Effective space is 16 MB.
Reserved	1 GB	801 4000 0000 801 7FFF FFFF
P-Chip0 CSR’s	256 MB	801 8000 0000 801 8FFF FFFF	addr[5:0]=0. Quadword access only.
Reserved	256 MB	801 9000 0000 801 9FFF FFFF
C-Chip CSR’s	256 MB	801 A000 0000 801 AFFF FFFF	addr[5:0]=0. Quadword access only. Non-cacheable.
D-Chip CSR’s	256 MB	801 B000 0000 801 BFFF FFFF	addr[5:0]=0. Each byte per quadword points at 1 of 8 D-Chips. All bytes must be identical. Non-cacheable
Reserved	896 MB	801 C000 0000 801 F7FF FFFF
P-Chip 0 PCI IACK/Special	64 MB	801 FC00 0000 801 FBFF FFFF	Linear addressing, No address extension using HAE
P-Chip 0 PCI I/O	32 MB	801 FC00 0000 801 FDFF FFFF	Linear addressing. No HAE. Non- cacheable.
P-Chip 0 PCI Configuration	16 MB	801 FE00 0000 801 FEFF FFFF	Linear addressing. No HAE. Non- cacheable.
Reserved	16 MB	801 FF00 0000 801 FFFF FFFF
P-Chip1 PCI Memory	4 GB	802 0000 0000 802 FFFF FFFF	Linear addressing,. Non-cacheable.
Reserved	2 GB	803 0000 0000 803 7FFF FFFF
P-Chip 1 CSR’s	256 MB	803 8000 0000 803 8FFF FFFF	Linear addressing, No HAE. Non- cacheable.
Reserved	1664 MB	803 9000 0000 803 F7FF FFFF
P-Chip1 PCI IACK/Special	64 MB	803 F800 0000 803 FBFF FFFF	Linear addressing, No HAE. Non- cacheable.
P-Chip 1 PCI I/O	32 MB	803 FC00 0000 803 FDFF FFFF	Linear addressing. No HAE. Non- cacheable.
P-Chip 1 Configuration	16 MB	803 FE00 0000 803 FEFF FFFF	Linear addressing. No HAE. Non cacheable.
Reserved	8188 GB	804 0000 0000 FFF FFFF FFFF

CPU to PCI Address Translation

The table referenced in the figure to translate the CPU Mask into PCI AD[1:0] and PCI BE[3:0] follows.

CPU to PCI I/O Space Address Translation

PCI Configuration Space 0 Mapping

The table referenced in figure to translate CPU Mask into PCI AD[1:0] and PCI BE[3:0] follows.

The decoding of the 5-bit Device # field in CPU Address to generate the field IDSEL[20:0] in PCI AD[31:11] is straightforward. The Device field is binary encoded with 00000 setting IDSEL[0] (which is PCI AD[11]), 00001 setting IDSEL[1] (PCI AD[12]) and so on up to 10100 setting IDSEL[20] (PCI AD[31]). Device field encodings 10101-11111 are unused and result in IDSEL[20:0] being all 0’s.

PCI Configuration Space 1 Mapping

TIG Address Space Translation

PCI DMA Address Translation

The P-Chips ignore the following PCI commands from a PCI device:

• Interrupt acknowledge
• Special Cycle
• I/O Read & Write
• Configuration Read & Write

Each P-Chip supports 4 DMA address windows and 1 DMA Monster window. Each of the normal DMA windows are capable of mapping to system memory or to other PCI assuming another P-Chip exists. Assuming the window selected by the PCI address is not a Peer-to-Peer window, it can translate the incoming address to the System Memory address in 2 ways, as follow.

1. Direct Mapped: The incoming address is compared against Window Base Address register and a Window Mask register which determines the size of the window. If the address falls in this window, the address bits that are not part of the compare are concatenated to a Translated Base address register to form the System Memory Address. Note that the PCI Address bits that are not part of the compare are the lower order bits and represent the size of the window.
   System Address[34:2] = T_Base[34:20+n]:PCI_AD[19+n:2]
   where n varies from 0-11. This means that size of the window can vary from 1 MB to 2 GB.

2. Scatter/Gather Mapping: This scheme also uses the Window Base, Window Mask and Translated Base Address Registers. The difference is that the translated address from the scheme for direct mapping results in a quadword address into a System Memory based page table which produces a Page Table Entry (PTE). The PTE produces the top 21 bits of the System memory address while the PCI AD[12:0] are sent through untranslated as the Page Offset. The translation is illustrated in the following figure.

Monster Window